1. Field of the Invention
The present invention relates to a semiconductor memory device having a crosspoint-type memory cell array in which memory cells are arranged in a row direction and a column direction, one ends of the respective memory cells in the same row are connected to the same row selection line, and the other ends of the respective memory cells are connected to the same column selection line. More particularly, the present invention relates to a semiconductor memory device in which a memory cell comprises a variable resistive element which stores three or more multi-level information depending on a change in electric resistance.
2. Description of the Related Art
Recently, a crosspoint-type semiconductor memory device (referred to as the “crosspoint memory” occasionally hereinafter) comprising a memory cell array in which a memory cell does not comprise a selection element and a memory element is directly connected to a row selection line (referred to as the “data line” hereinafter) and a column selection line (referred to as the “bit line” hereinafter) in a memory cell has been increasingly developed (refer to Japanese Unexamined Patent Publication No. 2002-8369, for example).
According to “Equivalent Voltage Detection Method for Resistive Cross Point Memory Cell Array” disclosed in the Japanese Unexamined Patent Publication No. 2002-8369, a predetermined voltage is supplied to each of the data line and bit line to detect a resistance state of a memory cell of an MRAM (Magnetic Random Access Memory). According to this patent document 1, when a selected memory cell is read, a resistance state, that is, a memory state of the selected memory cell is detected by applying a first voltage to a selected data line and applying a second voltage lower than the first voltage to selected and unselected bit lines and unselected data lines.
FIG. 15 shows a circuit constitution of a memory cell array of a conventional crosspoint memory, set levels of voltages applied to data lines and bit lines, and current paths. According to the crosspoint memory shown in FIG. 15, when a selected memory cell is read, a resistance state of the selected memory cell is detected by applying a third voltage V2 to a selected bit line and applying a fourth voltage V1 which is higher than the third voltage V2 to selected and unselected data lines and unselected bit lines.
FIG. 15 shows a case where when a resistance state of a memory cell positioned at an intersection of a data line D0 and a bit line B0 is read, the resistance state of the object memory cell is determined by reading a current of the selected data line D0.
FIG. 16 shows a voltage setting of each data line and bit line and current paths when the resistance value of memory cell positioned at the intersection of the data line D0 and bit line B0 is read on the side of the bit line. In FIG. 16, similar to the voltage setting in the above patent document 1, when the selected memory cell is read, a resistance state of the selected memory cell is detected by applying a first voltage V1 to a selected data line and applying a second voltage V2 lower than the first voltage V1 to selected and unselected bit lines and unselected data lines. In this case, the resistance state of the object memory cell is determined by reading a current of the selected bit line B0.
FIG. 17 shows paths of leak currents Ileak0, Ileak1, . . . Ileakk generated when a readout current Id of a memory cell Md is measured. Reference character M in FIG. 17 virtually shows an ampere meter which measures the current IM on the selected data line. In a readout state shown in FIG. 17, voltages applied to bit lines and data lines are set in the same manner as that shown in FIG. 15. In this case, the readout current Id of the memory cell Md is shown by the following equation (1). In addition, a symbol of operation Σi=0 to k shows an arithmetic sum in a range of i=0 to k.Id=IM −Σi=0 to k Ileaki  (1)
FIG. 18 shows paths and direction of the leak current Σi=0 to k Ileak1i generated when a readout current Id1 of a memory cell Md1 is measured, and direction of Σi =0 to k Ileak2i generated when a readout current Id2 of a memory cell Md2 is measured. In a readout state shown in FIG. 18, voltages applied to bit lines and data lines are set in the same manner as that shown in FIG. 15. In this case, when a resistance value of the memory cell Md1 is low in the memory cell connected to the selected bit line, a voltage of a data line D1 is lowered because of voltage division corresponding to a resistance division ratio of an ON resistance value of a driver which drives the data line and a resistance value of the memory cell Md1.
Therefore, since a voltage at a contact point d1A of the memory cell Md1 and the data line D1 is lower than the other data line voltages, leak currents flowing from the bit line to the memory cell Md1 are generated. That is, the leak current (sneak current through an unselected memory cell) Σi=0 to k Ileak1i is generated from the bit line to the memory cell Md1 through the data line D1. In this case, a relation between the readout current Id1 of the memory cell Md1 and a measured current IM1 in the data line D1 is shown by the following equation (2). Reference character M1 in FIG. 18 virtually shows an ampere meter which measures the current IM1.IM1=Id1−Σi=0 to k Ileak1i  (2)
In addition, when a resistance value of the memory cell Md2 is high in the memory cell connected to the selected bit line, a voltage of a data line D2 is raised because of voltage division corresponding to a resistance division ratio of an ON resistance value of the driver which drives the data line and a resistance value of the memory cell Md2.
Therefore, since a voltage at a contact point d2A of the memory cell Md2 and the data line D2 is higher than the other data line voltages, leak currents (sneak currents through unselected memory cells) Σi=0 to k Ileak2i flow from the data line D2 to the bit line. That is, the leak current Σi=0 to k Ileak2i is generated from the data line D2 to a memory cell Mdx connected to the data line through the bit line. In this case, a relation between the readout current Id2 of the memory cell Md2 and a measured current IM2 in the data line D2 is shown by the following equation (3). Reference character M2 in FIG. 18 virtually shows an ampere meter which measures the current IM2.IM2=Id2+Σi=0 to k Ileak2i  (3)
The reason why the leak current is generated depending on the resistance value of the memory cell to be read out is that an apparent resistance value exists in the data line and the bit line as shown in FIG. 19. More specifically, the apparent resistance value is a resistance value when the driver which drives the data line and the driver which drives the bit line are driven.
Specifically, FIG. 19 shows a case in which the voltages applied to the data line and the bit line are set in the same manner as that shown in FIG. 15. In order to set the voltages of the data line and the bit line, drivers A are needed as shown in FIG. 19. When the driver A is driven, the ON resistance (it is assumed that the resistance value is R) exists. When the resistance values of the memory cells on the selected bit line in the memory cell array, that is, R1, R2, R3 and R4 are different from each other, voltages Vdi (i=1 to 4) of the data lines 1 to 4 are shown by the following equation (4). In addition, it is assumed that V1 is a driving voltage of each data line and V2′ is a voltage of the selected bit line.Vdi=(V1−V2′)×Ri/(Ri+R)  (4)
As shown the equation (4), the voltage Vdi of each data line varies with Ri. Therefore, the voltage of the data line varies with the resistance value of the memory cell on the selected bit line and the leak current is generated.
FIG. 20 shows one example of a circuit serving as a data line driver and an amplifier. The circuit serving as the data line driver and the amplifier applies a predetermined voltage (power supply voltage Vcc, for example) to the selected and unselected data lines. A P channel MOSFET (referred to as the “PMOS” hereinafter) P0 in the circuit serving as the data line driver and the amplifier supplies a drive current Ix which accesses a memory cell from the data line. When the resistance value of the accessed memory cell is high, since a current supplied from the PMOS (P0) of the data line drive circuit in FIG. 20 to the memory cell array is reduced, the gate voltage of the PMOS is raised. Meanwhile, when the resistance value of the accessed memory cell is low, since a current supplied from the PMOS (P0) of the data line drive circuit in FIG. 20 to the memory cell array is increased, the gate voltage of the PMOS (PMOS) is lowered. The gate voltage of the PMOS (P0) is amplified by the PMOS (P1) and the load transistor (N channel MOSFET) in a data line current amplification circuit in FIG. 20 and the amplified voltage V0 is outputted.
FIG. 21 shows an example of the bit line drive circuit shown in FIG. 19. The bit line drive circuit comprise a load circuit P0 in a PMOS and a column selection circuit comprising two CMOS transfer gates. According to the column selection circuit, when the bit line is selected by a decode output of a column address decoder (column decoder), the right CMOS transfer gate in FIG. 21 is turned on, the ground voltage Vss is supplied to the bit line, and when the bit line is not selected, the left CMOS transfer gate in FIG. 21 is turned on and a voltage which drops from the power supply voltage Vcc by a threshold voltage of the PMOS (P0) is supplied. In addition, the voltage supplied to the bit line when the bit line is not selected is at the same voltage level as that of the voltage supplied to the data line.
As described above, the measured current IM1 in the data line D1 in FIG. 18 is as shown in the equation (2) and the measured current IM2 in the data line D2 in FIG. 18 is as shown in the equation (3). As shown in the equations (2) and (3), when the predetermined voltage is applied to the data line and the bit line at the time of readout using the conventional circuit serving as the data line driver and amplifier and the bit line driver, since the current direction of the leak current varies according to the resistance value of the memory cell to be read out, in the case the leak current value is great, it is difficult to lead the memory cell readout currents Id1 and Id2 from the measured currents IM1 and IM2 measured on the data line.
Especially, when the memory cell stores three or more multi-level information, it needs to further prevent variation in the measured current IM, IM1 or IM2 corresponding to each memory level measured on the data line, and controlling means for highly preventing the leak current value is needed.
Furthermore, in the case where the voltage level setting to read the resistance value of the memory cell on the bit line side shown in FIG. 16 is used, the current direction of the leak current when the resistance value of the selected memory cell is high is shown in FIG. 22.
In FIG. 22, when the resistance value of the selected memory cell is high, the direction of the memory cell current Id1 flowing in the bit line B0 is the same as that of the leak currents Ileak0, Ileak1, . . . Ileakk. In addition, as shown in FIG. 23, when the value is low, the direction of the memory cell current Id2 flowing in the bit line B0 is the opposite to that of the leak currents Ileak00, Ileak01, . . . Ileak0k. In this case, since the values of the measured current IM1 and IM2 largely vary with the leak current value, the memory cell currents Id1 and Id2 cannot be correctly detected. As shown in FIGS. 22 and 23, in the setting method of the voltages to the data line and bit line shown in FIG. 16, the leak current flows backward depending on the resistance value of the selected memory cell similar to the leak currents shown in FIGS. 17 and 18.
In this case also, when the memory cell stores three or more multi-level information, it needs to further prevent variation in the measured current IM, IM1 or IM2 corresponding to each memory level measured on the data line, and controlling means for highly preventing the leak current value is needed.
Next, a description will be made of a case where the memory cell array is accessed (selected) by the bank with reference to FIG. 24. FIG. 24 shows a constitution in which the memory cell array is divided into a plurality of banks. In this case, in addition to the ON resistance of the driver described with reference to FIG. 19, an ON resistance of an array selection transistor BSi is added. Therefore, the voltage fluctuation of the data line becomes large as compared with the single memory cell array constitution shown in FIG. 19. When a memory cell in the memory cell array 10 (bank 1) in FIG. 24 is read, it is necessary to turn on a transistor in a transistor column BS1 (bank selection transistor column) which selects the memory cell array 10 (bank 1). In addition, in order not to select other memory cell arrays MR0, MR2, and MR3 (banks 0, 2 and 3), it is necessary to turn off all transistors in array selection transistor columns BS0, BS2 and BS3. Thus, when the transistors in the array selection transistor column BS1 are turned on, ON resistances Rbs1, Rbs2, . . . , Rbsx of the transistors are provided on the data line. Therefore, a voltage Vdij of the data line in each bank shown in FIG. 24 is shown by the following equation (5), where “i” designates an order of the data line in the same bank, “j” designates an order of the bank, and “Rij” designates a resistance value of the memory cell connected to a selected bit line and i-th data line in a bank j.Vdij=(V1−V2′)×Rij/(Rij+R+Rbsj)  (5)
As shown in the equation (5), the voltage is more largely fluctuated than the voltage of the data line shown in the equation (4). That is, since the leak current caused by the voltage fluctuation of the data line is increased, when the memory cell stores three or more multi-level information especially, the influence of the leak current is increased and the readout of the memory cell becomes more difficult or becomes impossible.